Plano, Texas, USA – May 13 2025 – Siemens Digital Industries Software today announced the Questa™ One smart verification software portfolio, combining connectivity, a data driven approach and ...

Expands memory chipset offering to cover all JEDEC defined memory modules for servers and PCs ...

SMIC has had trouble with yields and output which will reduce this quarter's revenues by 6%, reports DigiTimes. The problems ...

The Synopsys IP Prototyping Kits, part of the IP Accelerated initiative, center around a complete, out-of-the-box reference design that consists of a validated IP configuration and necessary system-on ...

CELUS, the developer of an AI-assisted electronics design platform, has announced the integration of its CELUS Design Platform with the Cadence OrCAD X Platform, a comprehensive PCB design software ...

Our logiRECORDER Director, Jura Ivanovic presents our high bandwidth data logging demo, showing you how the XYLON QUATTRO solves the most advanced requirements of today’s automotive industry.

The rapid acceleration of semiconductor technologies is creating system-on-chip (SoC) devices that are increasingly complex. These chips contain billions of transistors and hundreds of functional ...

TSMC's new A14 process is already backed by certified EDA tools from Cadence, Synopsys, and Siemens to accelerate next-gen AI and chiplet-based designs.

The WEA7186F55 is a front end for wireless microwave transceivers operating in the E-Band. Implemented in a ST Micro Silicon Germanium B55 process. The WEA7186F55 integrates a LNA path, a Power ...

The A12B50M is an ultra low-power, pipeline analog to digital converter (ADC) intellectual property (IP) design block. It has 12-bit resolution and a sampling rate of up to 50 megasamples per second ...

Mobiveil’s PCIe Gen3 to SRIO Gen3 Bridge is a high-performance FPGA-based protocol conversion IP that enables seamless communication between PCI Express (PCIe) and Serial RapidIO (SRIO) systems.

By Abhishek BV, eInfochips Abstract: Since its inception, BCD technology has leveraged the integration of two primary technologies—polysilicon gate CMOS and DMOS power architecture—on the same chip.