资讯

CAMPBELL, Calif., May 13, 2025 -- Arteris, Inc. (Nasdaq: AIP), a leading provider of system IP which accelerates system-on-chip (SoC) creation, today announced financial results for the first quarter ...
With the chiplet architecture gaining momentum as a modular and scalable alternative to traditional monolithic SoCs, Secafy is leveraging Menta's eFPGA IP to add post-silicon flexibility, ...
eMemory's NeoEE IP is a cost-effective embedded EEPROM solution for both foundries & customers. No additional masks are required, and NeoEE gives foundry and customer many advantages such as fast time ...
Expands memory chipset offering to cover all JEDEC defined memory modules for servers and PCs ...
SMIC has had trouble with yields and output which will reduce this quarter's revenues by 6%, reports DigiTimes. The problems ...
Plano, Texas, USA – May 13 2025 – Siemens Digital Industries Software today announced the Questa™ One smart verification software portfolio, combining connectivity, a data driven approach and ...
The Synopsys IP Prototyping Kits, part of the IP Accelerated initiative, center around a complete, out-of-the-box reference design that consists of a validated IP configuration and necessary system-on ...
Logic Fruit Technologies has designed & implemented ARINC 818 Transmitter & Receiver IP Core supporting multiple line rates up to 4.25Gbps. The IP core has been developed by taking DO-254 Methodology ...
Mobiveil's 5G NR LDPC Decoder IP Core offers a robust solution for LDPC decoding, featuring a dedicated LDPC decoder block for optimal performance. It employs the Min-Sum LDPC decoding algorithm to ...
YEESTOR’ PCIe-NVMe SSD controller platform (Libra) is compliant with NVM Express specification and targets for both enterprise and client SSD markets. It features ...
The rapid acceleration of semiconductor technologies is creating system-on-chip (SoC) devices that are increasingly complex. These chips contain billions of transistors and hundreds of functional ...
Mobiveil’s PCIe Gen3 to SRIO Gen3 Bridge is a high-performance FPGA-based protocol conversion IP that enables seamless communication between PCI Express (PCIe) and Serial RapidIO (SRIO) systems.